Informatics Publishing Limited

K. P. Sridhar ¹, S. Saravanan ², R. Vijay Sai ²

Affiliations
1 VLSI Design, School of Computing, SASTRA University, Thanjavur, Tamil Nadu- 613401, IN
2 School of Computing, SASTRA University, Thanjavur, Tamil Nadu- 613401, IN

Abstract

Power attack is the most powerful side channel attacks in cryptography chip during VLSI (Very Large Scale Integration) testing. Hackers attack the target devices by means of power through finding the correlations between the power spikes for different input generated on Cathode Ray Oscilloscope (CRO). To overcome such a great issues we proposed the novel techniques for cryptography devices which perform their crypto functions without an external power source. Energy required to do the cryptographic operation is provided by Embedded Capacitance Power Supply (ECPS) method, which is integrated with the VLSI device. Group of capacitors are connected to form the power supply, which act as the temporary battery of the cryptographic chip. The power spikes for this crypto operation not visible by the CRO. Hence it is complicate for attackers to hack the crypto system. The proposed method is modelled through Hardware Description Language (HDL) Verilog-AMS using Switch Level Modelling and result is verified by simulation wave form generated.

Keywords

Cryptography Chip, Embedded Capacitance Power Supply, Side Channel Attack, Vlsi Testing

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M. Lavanya ¹, R. Vijay Sai ¹, A. Festina ², J. Eshwari ², T. Manopriya ², V. Vaithiyanathan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN
2 Information and Communication Technology, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

This article aims to focus on encryption based algorithm on ASCII value and Random number generator. Proposed algorithm has been developed with the view to achieve data security and prevent unauthorized persons from meddling with such secret data. An ASCII based conversion has been implemented to encrypt shorter length messages through a symmetric key. The algorithm specifically accommodates the concept of random number generation that makes it tough for the hackers to decrypt despite accidentally discovering the key. This concept also involves floating point numbers for encryption to enhance the difficulty level of cryptanalysis. Hence this algorithm will provide an efficient way to make it almost impossible for the intruders to track the message.

Keywords

ASCII, Encryption, Hackers, Random Number, Symmetric Key

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R. Vijay Sai ¹, S. Saravanan ¹, V. Anandkumar ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

This article shows the importance of security in memory for VLSI circuits based on data scrambling and overcome attacks. Security information stored in memory is very valuable. The model should not be prone to intruder attacks. The proposed method provides scrambling of information by data scrambling vectors. Instead of using some extra table for scrambling the data in cache memories, the data is divided into two halves and scrambled within to overcome extra hardware and memory requirement. This method is implemented in Verilog HDL using Model Sim which has improvement in area and memory requirement. This method is more suitable for value added applications such as smart cards and bio metric applications.

Keywords

Cache Read and Write Operations, Scrambling Vectors, Security in Memory

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M. S. Vandhana ¹, R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur -613401, Tamil Nadu, IN

Abstract

The channel scaling attains the overflow current at the transistor, which impacts on power indulgence. In order to attain reduced power and delay, the devices are assumed to decrease its size. Then transistors size can also be changed. In this paper the unique dynamic isolated read SRAM has been projected for dropping the total power. By linking, the cell with 6T and NC SRAM in numerous features, high constancy and decreased power is achieved by the curvature N (noise) method, which is done when the system is in active mode. The values are calculated with the voltage of 1.8 which reduces 90% of power than the 6T, and 18% of power is reduced than the 8T SRAM cell, and 30% of leakage current is reduced as compared to 6T cell. Thus when related to the existing SRAM, the cell consumes less power and without any distortion the cell stores the data. Also the constancy of the cell is improved when compared with the other cell. The waveform result shows that the cell attains enhanced stability and reduction in overflow using the cadence virtuoso technology of 180 nm.

Keywords

Curvature-noise, Stability, Static Current Noise Margin, Static Voltage Noise Margin, Write Trip Point.

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S. Manju Bharathi ¹, R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

Cache memories are revealed to transitory error in tag bits and some of the efforts have been taken to decrease their susceptibility. In the advanced mechanisms of cache memories are most applicable components, because the soft errors are protected. The identical tag bit data is used to regain from the error in the tag bits. In this paper, to improve error protection capacity of the tag bits in caches, power efficient cache design is proposed by using Superlative Standard Techniques (SST) architecture to achieve power. To utilize the identical tag bits for transitory error protection, the proposed scheme is discussed by selecting the energy superlative standard techniques that decrease unwanted interior activities by reducing the dynamic switching power. In experimental method, results show that our proposed multilevel cache architecture sustains a performance of achieving dynamic power and reduces the power consumption up to 85% when applied to energy optimal technique.

Keywords

Cache Memories, Identical Tag Information, Superlative Standard Techniques (SST), Tag Bits, Transitory Error.

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R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations. The objective of this review is to analyze various attacks targeting cache memory and suggest remedial measures to thwart such attacks and assure cache memory security. Methods/Statistical Analysis: Information stored in cache memory can be recovered whenever required. This data is in danger of being hacked by the intruder. Statistical analysis show that attacks such as side channel attacks, timing attacks and power based attacks are adopted to challenge information security in caches. Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested XOR operations, extended Hamming codes and multi-bit clustered ECC. Application/Improvements: Improving and authenticating cache memory security will result in numerous applications involving smart cards and bio-metric applications where secrecy of data is of extreme importance.

Keywords

Cache Memory, Power Based Attacks, Side Channel Attack, Timing Attacks.

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